1. Field of the Invention
This invention relates to a method for fabricating a via, and more particularly to a method for fabricating a via which can prevent via poisoning.
2. Description of Related Art
For semiconductor devices fabricated in very large scale integration (VLSI) technology, that is, within an area of 1-2 cm.sup.2, there are several hundred thousand transistors fabricated together. In order to achieve this kind of high integration fabrication, the density of interconnecting metal lines for connecting transistors is accordingly increased. In this case, using a single metal layer in the design is no longer adequate for interconnecting the transistors. It has instead gradually become a common strategy in the design of integrated circuits (ICs) to use at least two metal layers. Inter-metal dielectric layers are interposed between these metallic multiple layers, to isolate them. On an inter-metal dielectric layer, there is usually at least one via formed to reserve a space to connect these metallic multiple layers, in which a conductive material fills the via to form a plug and also forms the metal layer over the inter-metal dielectric layer. Through the plug, different metal layers are electrically coupled.
As the device dimensions get smaller, the device's increasing RC time delay becomes a performance-limiting factor. Materials with a low dielectric constant, such as the dielectric constant K is less that 4 can be integrated into devices to reduce the RC time delay and thereby improve device performance.
Recently, flowable oxide (FOx.TM.), a compound of hydrogen silsesquioxane (HSQ) manufactured by Dow Corning Corp. has been used to form the inter-metal dielectric layers. Fox, having low K of about 3, has a K smaller than the usual quantity of about 3.8-4.0 so that it is quite suitable for gap-filling, such as filling the via, and has gradually become a commonly used material in VLSI fabrication.
Because of the low dielectric constant of FOx, the problem of parasitic capacitance is reduced. The RC time delay therefore becomes shorter, and the device performance speed is higher. This low-K material has been successfully applied in sub-half-micron technology.
Although FOx has the advantages mentioned above, it has the drawback of being hydrophilic, and is therefore easily affected by humidity, reacting with water during the fabrication procedure to form a poisoned via. The successful application of FOx as an inter-metal dielectric after coating and curing depends on (1) exhaustive preservation of the Si-H bond content, (2) prevention of moisture absorbtion, and (3) careful tuning of via etching process, which includes oxygen plasma ashing and wet chemical stripping to have less degradation to the FOx layer and preserve its low-K property after subsequent processing. Of these above three, the oxygen plasma ashing and wet chemical stripping used in conventional photoresist-mask patterning technology are found to be the most likely to degrade and impair the dielectric property of the FOx material. The careful selection of oxygen plasma ashing and wet chemical stripping processes can lessen the degradation of the FOx material however, the surface of the FOx layer will inevitably be damaged.
The damage inside the via does not have to be a problem, since a low dielectric constant is mainly needed between interconnecting metal lines. Even so, the moisture absorption by the damaged FOx inside the via can create a poisoned via during subsequent high temperature plug-filling process.
FIGS. 1-3 are cross sectional views schematically illustrating the fabrication of a conventional via. The like reference numbers have like materials in FIGS. 1-3.
In FIG. 1, there are a semiconductor substrate 10, a metal layer 12, an oxide layer 14, a FOx layer 15, a glue layer 16, and a tungsten (W) conductive layer 18. Surface damage 19 of the via 20 is shown. A void 17, which causes the via 20 to be poisoned, is formed because the moisture absorbed by the FOx layer 15 is released during subsequent high temperature plug-filling process and, therefore, the W conductive layer 18 can not fully fill the via 20.
Referring to FIG. 2, in order to avoid forming a poisoned via 20 due to a void 17 as shown in FIG. 1, or a volcano-like structure due to an explosion of bubbles during deposition of the W conductive layer 18, furnace baking and degassing processes are necessary to get rid of absorbed moisture in the exposed FOx material inside a via 21 before the glue layer 16 is deposited. The glue layer 16, including Ti/TiN, is deposited before the W conductive layer 18 plug-fill is formed. The degassing process can be finished in a degassing chamber and then the whole chip/wafer/piece/operation can be vacuum-transferred to Ti/TiN sputter deposition chambers of the same sputter-machine mainframe without absorbing more moisture due to vacuum-break. A robust and unpoisoned via 21 is therefore formed.
In the case of FIG. 2 described above, the method for preventing via poisoning is suitable for a technology with a dimension of 0.35 .mu.m but is not suitable for a technology with a dimension smaller than 0.25 .mu.m. It is limited by the formation of a photolithography window. An unlanded via fabrication process is needed to replace the formation of the photolithography window. Because the alignment of the via in the unlanded fabrication process is not strictly required, that the via is allowed to have a little portion the does not overlap the metal layer.
In FIG. 3, an unlanded via 22 is not fully formed over the metal layer 12. In this case, the inner surface of the unlanded via 22 exposes a large area of the damaged FOx layer. Although proper furnace baking and degas processes are performed, the only effect is releasing the absorbed moisture. The FOx layer could be punched through during subsequent etching to form the unlanded via 22. Furthermore, the profile of the unlanded via 22 cannot be properly maintained. The unlanded via 22 is then inevitably poisoned during the subsequent processes of forming the glue layer 16 and etching back.